For automatic logic test pattern generation in manufacturing tests, the inputs and outputs of random access memories (RAMs) are exercised at speed to ensure that there are no delay faults on the logic paths into and out of the RAMs. During the tests, the contents of the RAMs on a chip are generally assumed to be unknown. Otherwise, the test generator would require extra processor time and memory to compute and remember RAM contents from one test sequence to the next, and the test sequences could not be reordered or applied individually at the tester. Typically for logic tests, the RAMs are put in a bypass mode so known, predictable data is launched from the RAM outputs.
However, to exercise the logic paths into and out of the RAMs, the bypass mode cannot be used. The RAMs must be in a functional mode so the tests can write to and read from the memories. The initial, unknown data, frequently called “X states,” that is outputted from the RAMs cannot be compressed into a verifiable signature, since the data is unknown.